In present semiconductor technology, CMOS devices, such as n-FETs and p-FETs, are typically fabricated upon semiconductor wafers that each has a substrate surface oriented along one of a single set of equivalent crystal planes of the semiconductor material (e.g., Si) that forms the substrate. In particular, most of today's semiconductor devices are built upon silicon wafers having wafer surfaces oriented along one of the {100} crystal planes of silicon.
Electrons are known to have a high mobility in the {100} crystal planes of silicon, but holes are known to have high mobility in the {110} or {111} crystal planes of silicon. On one hand, electron mobility in the {110} surfaces is significantly degraded compared to those in the {100} or {111} surfaces. On the other hand, hole mobility in the {110} ({111}) silicon surfaces is about 2 (1.5) times higher than that along the {100} silicon surfaces.
As can be deduced from the above, the {110} or {111} silicon surfaces are optimal for forming p-FET devices due to the excellent hole mobility along the {110} planes, which leads to higher drive currents in the p-FETs. However, such surfaces are completely inappropriate for forming n-FET devices. The {100} silicon surfaces instead are optimal for forming n-FET devices due to the enhanced electron mobility in the {100} planes, which results in higher drive currents in the n-FETs. Correspondingly, it is desirable to provide a semiconductor substrate having different surface orientations (i.e., hybrid surface orientations) that provide optimal performance for both the n-FETs and p-FETs in the CMOS circuit.
U.S. patent application Publication No. 2004/0256700 for “HIGH PERFORMANCE CMOS SOI DEVICES ON HYBRID CRYSTAL-ORIENTED SUBSTRATES” and U.S. patent application Publication No. 2005/0045995 for “ULTRA-THIN SILICON-ON-INSULATOR AND STRAINED-SILICON-DIRECT-ON-INSULATOR WITH HYBRID CRYSTAL ORIENTATIONS” have described formation of semiconductor substrates with hybrid surface orientations by wafer bonding, etching, and selective epitaxial regrowth techniques.
However, it is difficult and expensive to use wafer bonding, etching, and selective epitaxial regrowth techniques to manufacture semiconductor substrates with hybrid surface orientations that are suitable for forming semiconductor devices with narrow channel widths, such as, for example, the metal-oxide-semiconductor field effect transistors (MOSFETs) in static random access memory (SRAM) cells. Further, the selective epitaxial growth of silicon generates dislocation defects in the silicon crystal structures, which significantly undermine the device performance.
There is therefore a continuing need for improved substrates with hybrid surface orientations that can be fabricated at reduced costs with little or no dislocation defects.